As shown in FIG. 1, a typical computer system 10 has, among other components, a microprocessor 12, one or more forms of memory 14, integrated circuits 16 having specific functionalities, and peripheral computer resources (not shown), e.g., monitor, keyboard, software programs, etc. These components communicate with one another via communication paths 18, e.g., wires, buses, etc., to accomplish the various tasks of the computer system 10.
When an integrated circuit (16 in FIG. 1) communicates with another integrated circuit, i.e., xe2x80x9cchip-to-chip communication,xe2x80x9d data is transmitted in a series of binary 0""s and 1""s from a transmitting circuit to a receiving circuit. Accordingly, at any particular time, a data signal received at the receiving circuit may have a low voltage potential representative of a binary xe2x80x980 xe2x80x99 or a high voltage potential representative of a binary xe2x80x981.xe2x80x99
FIG. 2 shows a portion of a typical transmission system 20. The transmission system 20 includes a transmitting circuit 22, a data channel (also known as a xe2x80x9cboard tracexe2x80x9d) 24, and a receiving circuit 26. Generally, circuit-to-circuit wireline communication occurs by one circuit transmitting data and another circuit receiving the data over wires implemented on a computer board on which the sending and receiving circuits are disposed. As shown in FIG. 2, the transmitting circuit 22 drives data into the data channel 24 using the a driver stage 28 formed by a first driver 30 and a second driver 32. The receiving circuit 26 receives the data at the other end of the data channel 24 using some receiving device 34.
As mentioned above, in data signaling, a data bit is driven into the data channel 24 using specific voltage levels, i.e., logic high and logic low. In binary transmission, in which data is coded as a series of 1""s and 0""s, a xe2x80x981xe2x80x99 could be represented by any voltage above a particular value and a xe2x80x980xe2x80x99 could be represented by any voltage below a particular value.
FIG. 3 shows a schematic of the driver stage 28 shown in FIG. 2. The first driver 30 is formed using a pull-up device 36 and a pull-down device 38, and the second driver 32 is formed using a pull-up device 40 and a pull-down device 42. Those skilled in the art will understand that the inputs to the driver 30 and the second driver 32 are controlled separately in order to control, among other things, crow bar currents and voltage swing levels on the data channel 24. When activated, each of the pull-up and pull-down devices 36, 38, 40, and 42 effectively form a resistance, and when deactivated, each of the pull-up and pull-down devices 36, 38, 40, and 42 form an open circuit, or +infinite resistance.
FIG. 4 shows different states of the driver stage 28. When the driver stage 28 drives a xe2x80x981,xe2x80x99 the pull-up devices 36 and 40 of the first and second drivers 30 and 32, respectively, are switched xe2x80x98on,xe2x80x99 or otherwise activated, and the pull-down devices 38 and 42 of the first and second drivers 30 and 32, respectively, are switched xe2x80x98off,xe2x80x99 or otherwise deactivated. This arrangement of the pull-up and pull-down devices 36, 38, 40, and 42 causes the driver stage 28 to pull up the voltage value on the data channel 24.
Alternatively, when the driver stage 28 drives a xe2x80x980,xe2x80x99 the pull-down devices 38 and 42 of the first and second drivers 30 and 32, respectively, are switched xe2x80x98on,xe2x80x99 or otherwise activated, and the pull-up devices 36 and 40 of the first and second drivers 30 and 32, respectively, are switched xe2x80x98off,xe2x80x99 or otherwise deactivated. This arrangement of the pull-up and pull-down devices 36, 38, 40, and 42 causes the driver stage 28 to pull down the voltage value on the data channel 24.
As discussed with reference to FIG. 4, the driver stage 28, when driving a xe2x80x981,xe2x80x99 places a voltage step on the data channel 24. However, because the data channel 24 is typically lossy at high frequencies, the voltage step generated by the driver stage 28 suffers skin effect and dielectric loss. Losses in long data channels do not only introduce attenuation of data signal integrity, but more significantly, cause signal distortion. Such distortion results in intersymbol interference (ISI), which is described below.
A significant factor in achieving the highest possible data rate relates to the signal to noise ratio present at the receiving circuit. The noise present at the receiving circuit includes noise introduced by the data channel and noise attributable to interference from preceding bits of data. Such interference is ISI. ISI is a distortion in the received signal resulting from the temporal spreading and consequent overlap of individual signal pulses and to the degree that the receiving circuit cannot reliably distinguish between changes of state. It follows that at a certain threshold, intersymbol interference compromises the integrity of the data signal at the receiving circuit.
All of the effects discussed above that result from signal attenuation along the data channel leads to data jitter, which means that data does not reach a receiving circuit at the same time with respect to a clock signal for every data bit sent. This leads to uncertainty in data capture at the receiving circuit. Moreover, when a series of 1""s or 0""s are transmitted over a long data channel, jitter is amplified because the voltage swing at the receiving circuit increases or decreases depending on the number of consecutive 1""s or 0""s transmitted.
To this end, FIG. 5 shows a behavior of a data signal 50 in the transmission system 20 shown in FIG. 2 and using a driver stage 28 as described with reference to FIGS. 3 and 4. In the bit sequence shown in FIG. 5, the transmittal of the first four bits, xe2x80x980101,xe2x80x99 to the data channel (24 in FIGS. 2, 3, and 4) from the driver stage (28 in FIGS. 2, 3, and 4) occurs by switching the state of the driver stage (28 in FIGS. 2, 3, and 4) between the xe2x80x980xe2x80x99 arrangement and xe2x80x981xe2x80x99 arrangement shown in FIG. 4. The next several bits transmitted by the driver stage (28 in FIGS. 2, 3, and 4) are 0""s, and thus, the driver stage (28 in FIGS. 2, 3, and 4) remains in the xe2x80x980xe2x80x99 arrangement shown in FIG. 4 for some amount of time.
As shown in FIG. 5, as the driver stage (28 in FIGS. 2, 3, and 4) remains in the xe2x80x980xe2x80x99 arrangement shown in FIG. 4, the data signal 50 drifts to a voltage value below the xe2x80x980xe2x80x99 threshold. Then, when the driver stage (28 in FIGS. 2, 3, and 4) is again required to transmit a xe2x80x981,xe2x80x99 the voltage step driven onto the data channel (24 in FIGS. 2, 3, and 4) by the driver stage (28 in FIGS. 2, 3, and 4) results in the data signal 50 reaching a voltage value less than that reached previously when driving a xe2x80x981.xe2x80x99 Accordingly, as discussed above, such signal attenuation leads to ISI and increased data jitter.
FIG. 6 shows a behavior of a data signal 51 in the transmission system 20 shown in FIG. 2 and using a driver stage 28 as described with reference to FIGS. 3 and 4. In the bit sequence shown in FIG. 6, the transmittal of the first four bits, xe2x80x980101,xe2x80x99 to the data channel (24 in FIGS. 2, 3, and 4) from the driver stage (28 in FIGS. 2, 3, and 4) occurs by switching the state of the driver stage (28 in FIGS. 2, 3, and 4) between the xe2x80x980xe2x80x99 arrangement and xe2x80x981xe2x80x99 arrangement shown in FIG. 4. The next several bits transmitted by the driver stage (28 in FIGS. 2, 3, and 4) are 1""s, and thus, the driver stage (28 in FIGS. 2, 3, and 4) remains in the xe2x80x981xe2x80x99 arrangement shown in FIG. 4 for some amount of time.
As shown in FIG. 6, as the driver stage (28 in FIGS. 2, 3, and 4) remains in the xe2x80x981xe2x80x99 arrangement shown in FIG. 4, the data signal 51 drifts to a voltage value above the xe2x80x981xe2x80x99 threshold. Then, when the driver stage (28 in FIGS. 2, 3, and 4) is again required to transmit a xe2x80x980,xe2x80x99 the voltage drop driven onto the data channel (24 in FIGS. 2, 3, and 4) by the driver stage (28 in FIGS. 2, 3, and 4) results in the data signal 51 reaching a voltage value greater than that reached previously when driving a xe2x80x980.xe2x80x99 Accordingly, similar to the situation discussed with reference to FIG. 5, such signal attenuation leads to ISI and increased data jitter.
According to one or more embodiments of the present invention, a transmission system comprises: a driver stage operatively connected to a data channel, where the driver stage comprises a primary driver arranged to induce a first current flow in the driver stage dependent upon detection of a first data bit to be transmitted to the data channel, and a secondary driver arranged to reduce the first current flow dependent upon detection of a second data bit to be transmitted to the data channel, where the first data bit is logically equal to the second data bit; and a receiving circuit operatively connected to the data channel.
According to one or more embodiments of the present invention, a method for transmitting a data signal using a driver circuit comprises: detecting for a pattern of bits on the data signal; when consecutive bits of the same value are detected, inducing partial current flow in the driver circuit in a direction opposite to a flow of current induced by the driver circuit when the first of the consecutive bits was detected; and transmitting the data signal.
According to one or more embodiments of the present invention, an apparatus comprises: means for propagating a signal between at least two circuits; means for driving the signal onto the means for propagating, where the means for driving comprises primary means for driving on the signal a first bit, where a first flow of current is induced in the means for driving when driving the first bit, and secondary means for reducing the first flow of current in the means for driving when a second bit of the same logic value as the first bit is transmitted; and means for receiving the data signal.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.